Product Features

• Core

  ▆ 32-bit Arm® Cortex®-M0+ processor core

  ▆ Up to 60 MHz operating frequency

  ▆ Single-cycle multiplication

  ▆ Integrated Nested Vectored Interrupt Controller (NVIC)

  ▆ 24-bit SysTick timer

  The Cortex®-M0+ processor is a very low gate count, highly energy efficient processor that is  intended for microcontroller and deeply embedded applications that require an area optimized,  low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb® instruction sets; single-cycle I/O port; hardware multiplier and low latency interrupt respond time.

• On-chip Memory

  ▆ 64 KB on-chip Flash memory for instruction/data and options storage

  ▆ 16 KB on-chip SRAM

  ▆ Supports multiple boot modes

  The Arm® Cortex®-M0+ processor accesses and debug accesses share the single external interface  to external AHB peripheral. The processor accesses take priority over debug accesses. The  maximum address range of the Cortex®-M0+ is 4 GB since it has a 32-bit bus address width.  Additionally, a pre-defined memory map is provided by the Cortex®-M0+ processor to reduce  the software complexity of repeated implementation by different device vendors. However, some  regions are used by the Arm® Cortex®-M0+ system peripherals. Refer to the Arm® Cortex®-M0+  Technical Reference Manual for more information. Figure 2 shows the memory map of the  HT32F0008 device, including code, SRAM, peripheral, and other pre-defined regions.

• Flash Memory Controller – FMC

  ▆ Flash accelerator for maximum efficiency

  ▆ 32-bit word programming with In System Programming Interface (ISP) and In Application  Programming (IAP)

  ▆ Flash protection capability to prevent illegal access

  The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer  for the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower  than the CPU, a wide access interface with a pre-fetch buffer and cache are provided for the Flash  Memory in order to reduce the CPU waiting time which will cause CPU instruction execution  delays. Flash Memory word program/page erase functions are also provided.

• Reset Control Unit – RSTCU

  ▆ Supply supervisor:

  ● Power On Reset / Power Down Reset – POR/PDR

  ● Brown-out Detector – BOD

  ● Programmable Low Voltage Detector – LVD

  The Reset Control Unit, RSTCU, has three kinds of reset, a power on reset, a system reset and an  APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.  A system reset resets the processor core and peripheral IP components with the exception of the  SW-DP controller. The resets can be triggered by an external signal, internal events and the reset  generators.

• Clock Control Unit – CKCU

  ▆ External 4 to 16 MHz crystal oscillator

  ▆ External 32,768 Hz crystal oscillator

  ▆ Internal 8 MHz RC oscillator trimmed to ±2 % accuracy at 3.3 V operating voltage and 25 ˚C operating temperature

  ▆ Internal 32 kHz RC oscillator

  ▆ Integrated system clock PLL and USB PLL

  ▆ Independent clock divider and gating bits for peripheral clock sources

  The Clock Control Unit, CKCU, provides a range of oscillator and clock functions. These include  a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low  Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase Lock  Loop (PLL), a HSE clock monitor, clock prescalers, clock multiplexers, APB clock divider and gating  circuitry. The AHB, APB and Cortex®-M0+ clocks are derived from the system clock (CK_SYS)  which can come from the HSI, HSE or PLL. The Watchdog Timer and Real Time Clock (RTC) use  either the LSI or LSE as their clock source.

• Power Management – PWRCU

  ▆ Single VDD power supply: 1.65 V to 3.6 V

  ▆ Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply

  ▆ VDD power supply for RTC

  ▆ Two power domains: VDD, 1.5 V

  ▆ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down

  Power consumption can be regarded as one of the most important issues for many embedded  system applications. Accordingly the Power Control Unit, PWRCU, in the device provides many  types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down mode.  These operating modes reduce the power consumption and allow the application to achieve the best  trade-off between the conflicting demands of CPU operating time, speed and power consumption.

• External Interrupt/Event Controller – EXTI

  ▆ Up to 16 EXTI lines with configurable trigger source and type

  ▆ All GPIO pins can be selected as EXTI trigger source

  ▆ Source trigger type includes high level, low level, negative edge, positive edge, or both edge

  ▆ Individual interrupt enable, wakeup enable and status bits for each EXTI line

  ▆ Software interrupt trigger mode for each EXTI line

  ▆ Integrated deglitch filter for short pulse blocking

  The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate  a wake-up event or interrupt requests independently. Each EXTI line can also be masked  independently

• I/O Ports – GPIO

  ▆ Up to 42 GPIOs

  ▆ Port A, B, C, F are mapped as 16 external interrupts – EXTI

  ▆ Almost all I/O pins have a configurable output driving current

  There are up to 42 General Purpose I/O pins, GPIO, named from PA0 ~ PA15 to PC0 ~ PC7 and  PF0 ~ PF1 for the implementation of logic input/output functions. Each of the GPIO ports has  a series of related control and configuration registers to maximize flexibility and to meet the  requirements of a wide range of applications.

  The GPIO ports are pin-shared with other alternative functions to obtain maximum functional  flexibility on the package pins. The GPIO pins can be used as alternative functional pins by  configuring the corresponding registers regardless of the input or output pins. The external  interrupts on the GPIO pins of the device have related control and configuration registers in the  External Interrupt Control Unit, EXTI.

• PWM Generation and Capture Timers – GPTM

  16-bit up, down, up/down auto-reload counter

  ▆ 16-bit programmable prescaler allowing counter clock frequency division by any factor between  1 and 65536

  ▆ Input Capture function

  ▆ Compare Match Output

  ▆ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

  ▆ Single Pulse Mode Output

  ▆ Encoder interface controller with two inputs using quadrature decoder

  The General Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare  Registers (CCRs), one 16-bit Counter Reload Register (CRR) and several control/status registers.  They can be used for a variety of purposes including general time measurement, input signal pulse  width measurement, output waveform generation such as single pulse generation, or PWM output  generation. The GPTM supports an Encoder Interface using a decoder with two inputs.

• Pulse Width Modulation – PWM

  ▆ 16-bit up and auto-reload counter

  ▆ Up to 4 independent channels for each timer

  ▆ 16-bit programmable prescaler allowing counter clock frequency division by any factor between  1 and 65536

  ▆ Compare Match Output

  ▆ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

  ▆ Single Pulse Mode Output

  The Pulse Width Modulator consists of one 16-bit up/down-counter, four 16-bit Compare Registers  (CRs), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used  for a variety of purposes including general timer and output waveform generation such as single  pulse generation or PWM output.

• Basic Function Timer – BFTM

  ▆ 32-bit compare/match count-up counter – no I/O control features

  ▆ One shot mode – counting stops after a match condition

  ▆ Repetitive mode – restart counter after a match condition

  The Basic Function Timer is a simple count-up 32-bit counter designed to measure time intervals  and generate a one shot or repetitive interrupts. The BFTM operates in two functional modes,  repetitive or one shot mode. In the repetitive mode the BFTM restarts the counter when a compare  match event occurs. The BFTM also supports a one shot mode which forces the counter to stop  counting when a compare match event occurs.

• Watchdog Timer – WDT

  ▆ 12-bit down counter with 3-bit prescaler

  ▆ Reset event for the system

  ▆ Programmable watchdog timer window function

  ▆ Register write protection function

  The Watchdog Timer is a hardware timing circuit that can be used to detect system failures due  to software malfunctions. It includes a 12-bit count-down counter, a prescaler, a WDT delta value  register, WDT operation control circuitry and a WDT protection mechanism. If the software does  not reload the counter value before a Watchdog Timer underflow occurs, a reset will be generated  when the counter underflows. In addition, a reset is also generated if the software reloads the  counter when the counter value is greater than the WDT delta value. This means the counter must  be reloaded within a limited timing window using a specific method. The Watchdog Timer counter  can be stopped while the processor is in the debug mode. There is a register write protect function  which can be enabled to prevent it from changing the Watchdog Timer configuration unexpectedly.

• Real Time Clock – RTC

  ▆ 24-bit up-counter with a programmable prescaler

  ▆ Alarm function

  ▆ Interrupt and Wake-up event

  The Real Time Clock, RTC, includes an APB interface, a 24-bit count-up counter, a control  register, a prescaler, a compare register and a status register. Most of the RTC circuits are located in  the Backup Domain except for the APB interface. The APB interface is located in the VDD15 power  domain. Therefore, it is necessary to be isolated from the ISO signal that comes from the power  control unit when the VDD15 power domain is powered off, that is when the device enters the PowerDown mode. The RTC counter is used as a wakeup timer to generate a system resume signal from  the Power-Down mode.

• Inter-integrated Circuit – I2 C

  ▆ Supports both master and slave modes with a frequency of up to 1 MHz

  ▆ Provide an arbitration function and clock synchronization

  ▆ Supports 7-bit and 10-bit addressing modes and general call addressing

  ▆ Supports slave multi-addressing mode with maskable address

  The I2 C is an internal circuit allowing communication with an external I2 C interface which is an  industry standard two line serial interface used for connection to external hardware. These two  serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I2 C module  provides three data transfer rates: (1) 100 kHz in the Standard mode, (2) 400 kHz in the Fast mode  and (3) 1 MHz in the Fast plus mode. The SCL period generation register is used to setup different  kinds of duty cycle implementations for the SCL pulse.

  The SDA line which is connected directly to the I2 C bus is a bi-directional data line between the  master and slave devices and is used for data transmission and reception. The I2 C also has an  arbitration detect function and clock synchronization to prevent situations where more than one  master attempts to transmit data to the I2 C bus at the same time.

• Serial Peripheral Interface – SPI

  ▆ Supports both master and slave mode

  ▆ Frequency of up to (fPCLK/2) MHz for the master mode and (fPCLK/3) MHz for the slave mode

  ▆ FIFO Depth: 8 levels

  ▆ Multi-master and multi-slave operation

  The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function  in both master and slave mode. The SPI interface uses 4 pins, which are the serial data input and  output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device  acts as a master device which controls the data flow using the SEL and SCK signals to indicate the  start of data communication and the data sampling rate. To receive a data byte, the streamed data  bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data  transmission is carried out in a similar way but in a reverse sequence. The mode fault detection  provides a capability for multi-master applications.ons.

• Universal Synchronous Asynchronous Receiver Transmitter – USART

  ▆ Supports both asynchronous and clocked synchronous serial communication modes

  ▆ Asynchronous operating baud rate clock frequency up to (fPCLK/16) MHz and synchronous operating rate clock frequency up to (fPCLK/8) MHz

  ▆ Full duplex communication

  ▆ Fully programmable serial communication characteristics including:

  ● Word length: 7, 8, or 9-bit character

  ● Parity: Even, odd, or no-parity bit generation and detection

  ● Stop bit: 1 or 2 stop bit generation

  ● Bit order: LSB-first or MSB-first transfer

  ▆ Error detection: Parity, overrun, and frame error

  ▆ Auto hardware flow control mode – RTS, CTS

  ▆ IrDA SIR encoder and decoder

  ▆ RS485 mode with output enable control

  ▆ FIFO Depth: 8 × 9 bits for both receiver and transmitter

  The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full  duplex data exchange using synchronous or asynchronous data transfer. The USART is used to  translate data between parallel and serial interfaces, and is commonly used for RS232 standard  communication. The USART peripheral function supports four types of interrupt including Line  Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt  and Time Out Interrupt. The USART module includes a transmitter FIFO, (TX_FIFO) and receiver  FIFO (RX_FIFO). The software can detect a USART error status by reading the Line Status  Register, LSR. The status includes the type and the condition of transfer operations as well as  several error conditions resulting from Parity, Overrun, Framing and Break events.

• Universal Asynchronous Receiver Transmitter – UART

  Asynchronous serial communication operating baud rate clock frequency up to (fPCLK/16) MHz

  ▆ Full duplex communication

  ▆ Fully programmable serial communication characteristics including:

  ● Word length: 7, 8, or 9-bit character

  ● Parity: Even, odd, or no-parity bit generation and detection

  ● Stop bit: 1 or 2 stop bit generation

  ● Bit order: LSB-first or MSB-first transfer

  ▆ Error detection: Parity, overrun, and frame error

  The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data  exchange using asynchronous transfer. The UART is used to translate data between parallel and  serial interfaces, and is commonly used for RS232 standard communication. The UART peripheral  function supports Line Status Interrupt. The software can detect a UART error status by reading  the Line Status Register, LSR. The status includes the type and the condition of transfer operations  as well as several error conditions resulting from Parity, Overrun, Framing and Break events.

• Cyclic Redundancy Check – CRC

  Support CRC16 polynomial: 0x8005, X16+X15+X2 +1

  ▆ Support CCITT CRC16 polynomial: 0x1021, X16+X12+X5 +1

  ▆ Support IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X32+X26+X23+X22+X16+X12+X11+X10+X8 +X7 +X5 +X4 +X2 +X+1

  ▆ Supports 1's complement, byte reverse & bit reverse operation on data and checksum

  ▆ Supports byte, half-word & word data size

  ▆ Programmable CRC initial seed value

  ▆ CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit  data

  ▆ Supports PDMA to complete a CRC computation of a block of memory

  The CRC calculation unit is an error detection technique test algorithm which is used to verify  data transmission or storage data correctness. A CRC calculation takes a data stream or a block  of data as its input and generates a 16-bit or 32-bit output remainder. Ordinarily, a data stream is  suffixed by a CRC code and used as a checksum when being sent or stored. Therefore, the received  or restored data stream is calculated by the same generator polynomial as described above. If the  new CRC code result does not match the one calculated earlier, then this means that the data stream  contains a data error.

• Peripheral Direct Memory Access – PDMA

  ▆ 6 channels with trigger source grouping

  ▆ 8-/16-/32-bit width data transfer

  ▆ Supports Address increment, decrement or fixed mode

  ▆ 4-level programmable channel priority

  ▆ Auto reload mode

  ▆ Supports trigger source: SPI, USART, UART, I2 C, GPTM, PWM, AES and software request

  The Peripheral Direct Memory Access controller, PDMA, moves data between the peripherals  and the system memory on the AHB bus. Each PDMA channel has a source address, destination  address, block length and transfer count. The PDMA can exclude the CPU intervention and avoid  interrupt service routine execution. It improves system performance as the software does not need  to connect each data movement operation.

• Hardware Divider – DIV

  ▆ Signed/unsigned 32-bit divider

  ▆ Operation in 8 clock cycles, Load in 1 clock cycle.

  ▆ Divide by zero error Flag.

  The divider is the truncated division and need software trigger start single by control register"START" bit , after 8 clock cycles, the divider calculate complete flag will be set to 1, and if divisor  register data is zero, divide zero error flag will be set to 1.

• Universal Serial Bus Device Controller – USB

  ▆ Complies with USB 2.0 full-speed (12 Mbps) specification

  ▆ On-chip USB full-speed transceiver

  ▆ 1 control endpoint (EP0) for control transfer

  ▆ 3 single-buffered endpoints for bulk and interrupt transfer

  ▆ 4 double-buffered endpoints for bulk, interrupt and isochronous transfer

  ▆ 1,024 bytes EP_SRAM used as the endpoint data buffers

  The USB device controller is compliant with the USB 2.0 full-speed specification. There is one  control endpoint known as Endpoint 0 and seven configurable endpoints. A 1024-byte SRAM  is used as the endpoint buffer. Each endpoint buffer size is programmable using corresponding  registers, which provides maximum flexibility for various applications. The integrated USB fullspeed transceiver helps to minimize the overall system complexity and cost. The USB functional  block also contains the resume and suspend feature to meet the requirements of low-power  consumption.

• Advanced Encryption Standard – AES-128

  ▆ Supports AES Encrypt / Decrypt Function

  ▆ Supports AES ECB/CBC/CTR mode

  ▆ Supports Key Size 128 bits

  ▆ Supports 4 words Initial Vector for CBC and CTR mode

  ▆ 4 × 32 bits AES data buffer

  ▆ Supports DMA Interface

  ▆ Supports Word Data Swap Function

  The AES core supports encryption and decryption function. AES only supports 128 bits input data  to do encryption or decryption. Hardware does not pad any bits of input data. Software need to do  pad action at first.

• Debug Support

  ▆ Serial Wire Debug Port – SW-DP

  ▆ 4 comparators for hardware breakpoint or code / literal patch

  ▆ 2 comparators for hardware watchpoints

• Package and Operation Temperature

  ▆ 24/33/46-pin QFN, 48-pin LQFP package

  ▆ Operation temperature range: -40 ˚C to +85 ˚C