Product Features

• Core

  ▆ 32-bit Arm® Cortex®-M3 processor core

  ▆ Up to 96 MHz operating frequency

  ▆ Single-cycle multiplication and hardware division

  ▆ Integrated Nested Vectored Interrupt Controller (NVIC)

  ▆ 24-bit SysTick timer

  The Cortex®-M3 processor is a general-purpose 32-bit processor core especially suitable for products  requiring high performance and low power consumption microcontrollers. It offers many special  features such as a Thumb-2 instruction set, hardware divider, low latency interrupt respond time,  atomic bit-banding access and multiple buses for simultaneous accesses. The Cortex®-M3 processor  is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets.

• On-chip Memory

  ▆ 256 KB on-chip Flash memory for instruction/data and option storage

  ▆ Up to 128 KB on-chip SRAM

  ▆ Supports multiple boot modes

  The Arm® Cortex®-M3 processor is structured using Harvard architecture which uses a separate  bus structure to fetch instructions and load/store data. The instruction code and data are both  located in the same memory address space but in different address ranges. The maximum address  range of the Cortex®-M3 is 4 GB due to its 32-bit bus address width. Additionally, a pre-defined  memory map is provided by the Cortex®-M3 processor to reduce the software complexity of  repeated implementation for different device vendors. However, some regions are used by the  Arm® Cortex®-M3 system peripherals. Refer to the Arm® Cortex®-M3 Technical Reference Manual  for more information. Figure 2 shows the memory map of the HT32F12365/12366/22366 series of  devices, including Code, SRAM, peripheral, and other pre-defined regions.

• Flash Memory Controller – FMC

  ▆ Flash accelerator for maximum efficiency

  ▆ 32-bit word programming with In System Programming Interface (ISP) and In Application  Programming (IAP)

  ▆ Flash protection capability to prevent illegal access

  The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer  for the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower  than the CPU, a wide access interface with a pre-fetch buffer and cache are provided for the Flash  Memory in order to reduce the CPU waiting time which will cause CPU instruction execution  delays. Flash Memory word program/page erase functions are also provided.

• Reset Control Unit – RSTCU

  ▆ Supply supervisor:

  ● Power On Reset / Power Down Reset – POR/PDR

  ● Brown-out Detector – BOD

  ● Programmable Low Voltage Detector – LVD

  The Reset Control Unit, RSTCU, has three kinds of reset, a power on reset, a system reset and an  APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.  A system reset resets the processor core and peripheral IP components with the exception of the  SWJ-DP controller. The resets can be triggered by an external signal, internal events and the reset  generators.

• Clock Control Unit – CKCU

  ▆ External 4 to 16 MHz crystal oscillator

  ▆ External 32.768 kHz crystal oscillator

  ▆ Internal 8 MHz RC oscillator trimmed to ±2% accuracy at 3.3 V operating voltage and 25°C  operating temperature

  ▆ Internal 32 kHz RC oscillator

  ▆ Integrated system clock PLL

  ▆ Independent clock divider and gating bits for peripheral clock sources

  The Clock Control unit, CKCU, provides a range of oscillator and clock functions. These include  a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a  Low Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase  Lock Loop (PLL), a HSE clock monitor, clock prescalers, clock multiplexers, APB clock divider  and gating circuitry. The clocks of the AHB, APB and Cortex®-M3 are derived from the system  clock (CK_SYS) which can come from the LSI, LSE, HSI, HSE or PLL. The Watchdog Timer and  Real Time Clock (RTC) use either the LSI or LSE as their clock source. The maximum operating  frequency of the system core clock (CK_AHB) can be up to 96 MHz.

• Power Management – PWRCU

  ▆ Single VDD power supply: 2.0 V to 3.6 V

  ▆ Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply

  ▆ VBAT battery power supply for RTC and backup registers

  ▆ Three power domains: VDD, 1.5V and Backup

  ▆ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down

  Power consumption can be regarded as one of the most important issues for many embedded  system applications. Accordingly the Power Control Unit, PWRCU, in these devices provides many  types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down mode.  These operating modes reduce the power consumption and allow the application to achieve the best  trade-off between the conflicting demands of CPU operating time, speed and power consumption.

• External Interrupt/Event Controller – EXTI

  ▆ Up to 16 EXTI lines with configurable trigger source and type

  ▆ All GPIO pins can be selected as EXTI trigger source

  ▆ Source trigger type includes high level, low level, negative edge, positive edge, or both edge

  ▆ Individual interrupt enable, wakeup enable and status bits for each EXTI line

  ▆ Software interrupt trigger mode for each EXTI line

  ▆ Integrated deglitch filter for short pulse blocking

  The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate  a wake-up event or interrupt requests independently. Each EXTI line can also be masked  independently.

• Analog to Digital Converter – ADC

  ▆ 12-bit SAR ADC engine

  ▆ Up to 1 Msps conversion rate

  ▆ Up to 16 external analog input channels

  ▆ Conversion range: VREF+ ~ VREF-

  A 12-bit multi-channel ADC is integrated in the device. There are multiplexed channels, which  include 16 external analog signal channels and 2 internal channels can be measured. If the input  voltage is required to remain within a specific threshold window, an Analog Watchdog function  will monitor and detect these signals. An interrupt will then be generated to inform the device  that the input voltage is not within the preset threshold levels. There are three conversion modes  to convert an analog signal to digital data. The ADC can be operated in one shot, continuous and  discontinuous conversion modes.

• Analog Comparator – CMP

  ▆ Two rail-to-rail comparators

  ▆ Each comparator has configurable negative inputs used for flexible voltage selection

  ▆ Dedicated I/O pin or internal voltage reference provided by 6-bit scaler

  ▆ Programmable hysteresis

  ▆ Programming speed and consumption

  ▆ Comparator output can be output to I/O or to timers or ADC trigger inputs

  ▆ 6-bit scaler can be configurable to dedicated I/O for voltage reference

  ▆ Comparator has interrupt generation capability with wakeup MCU from Sleep or Deep Sleep  modes through the EXTI controller

  The two general purpose comparators (CMP) are implemented within the device. They can be  configured either as standalone comparators or combined with the different kinds of peripheral IP.  Each comparator is capable of asserting interrupts to the NVIC or wakeup the MCU Sleep or Deep  Sleep modes through EXTI wakeup event management unit.

• I/O Ports – GPIO

  ▆ Up to 80 GPIOs

  ▆ Port A, B, C, D, E are mapped as 16 external interrupts – EXTI

  ▆ Almost I/O pins are configurable output driving current

  There are up to 80 General Purpose I/O pins, GPIO, named from PA0 ~ PA15 to PE0 ~ PE15 for  the implementation of logic input/output functions. Each of the GPIO ports has a series of related  control and configuration registers to maximize flexibility and to meet the requirements of a wide  range of applications.

  The GPIO ports are pin-shared with other alternative functions to obtain maximum functional  flexibility on the package pins. The GPIO pins can be used as alternative functional pins by  configuring the corresponding registers regardless of the input or output pins.

  The external interrupts on the GPIO pins of the device have related control and configuration  registers in the External Interrupt Control Unit, EXTI.

• Motor Control Timer – MCTM

  ▆ Two 16-bit up, down, up/down auto-reload counters

  ▆ 16-bit programmable prescaler allowing division of the counter clock frequency by any factor  between 1 and 65536

  ▆ Input Capture function

  ▆ Compare Match Output

  ▆ PWM waveform generation with edge aligned and center-aligned Counting Modes

  ▆ Single Pulse Mode Output

  ▆ Complementary Outputs with programmable dead-time insertion

  ▆ Encoder interface controller with two inputs using quadrature decoder

  ▆ Supports 3-phase motor control and hall sensor interface

  ▆ Brake input to force the timer's output signals into a reset or fixed condition

  The Motor Control Timer consists of a single 16-bit up/down counter; four 16-bit CCRs (Capture/ Compare Registers), single 16-bit counter-reload register (CRR), single 8-bit repetition counter  and several control/status registers. It can be used for a variety of purposes including measuring  the pulse widths of input signals or generating output waveforms such as compare match outputs,  PWM outputs or complementary PWM outputs with dead-time insertion. The MCTM supports an  Encoder interface controller to an incremental encoder with two inputs. The MCTM is capable of  offering full functional support for motor control, hall sensor interfacing and brake input.

• General Purpose Timer – GPTM

  ▆ Two 16-bit up, down, up/down auto-reload counters

  ▆ 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor  between 1 and 65536

  ▆ Input Capture function

  ▆ Compare Match Output

  ▆ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

  ▆ Single Pulse Mode Output

  ▆ Encoder interface controller with two inputs using quadrature decoder

  The General-Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare  Registers (CCRs), one 16-bit Counter Reload Register (CRR) and several control/status registers.  They can be used for a variety of purposes including general time measurement, input signal pulse  width measurement, output waveform generation such as single pulse generation, or PWM output  generation. The GPTM supports an Encoder Interface using a decoder with two inputs.

• Basic Function Timer – BFTM

  ▆ Two 32-bit compare/match count-up counters - no I/O control features

  ▆ One shot mode – counting stops after a match condition

  ▆ Repetitive mode – restart counter after a match condition

  The Basic Function Timer is a simple count-up 32-bit counter designed to measure time intervals  and generate a one shot or repetitive interrupts. The BFTM operates in two functional modes,  repetitive or one shot mode. In the repetitive mode the BFTM restarts the counter when a compare  match event occurs. The BFTM also supports a one shot mode which forces the counter to stop  counting when a compare match event occurs.

• Watchdog Timer – WDT

  ▆ 12-bit down counter with 3-bit prescaler

  ▆ Interrupt or reset event for the system

  ▆ Programmable watchdog timer window function

  ▆ Register write protection function

  The Watchdog Timer is a hardware timing circuit that can be used to detect system failures due to  software malfunctions. It includes a 12-bit count-down counter, a prescaler, a WDT counter value  register, a WDT delta value register, interrupt related circuits, WDT operation control circuitry  and a WDT protection mechanism. The Watchdog Timer can be operated in an interrupt mode or  a reset mode. The Watchdog Timer will generate an interrupt or a reset when the counter counts  down and reaches a zero value. If the software does not reload the counter value before a Watchdog  Timer underflow occurs, an interrupt or a reset will be generated when the counter underflows. In  addition, an interrupt or reset is also generated if the software reloads the counter when the counter  value is greater than or equal to the WDT delta value. This means the counter must be reloaded  within a limited timing window using a specific method. The Watchdog Timer counter can be  stopped while the processor is in the debug mode. There is a register write protect function which  can be enabled to prevent it from changing the Watchdog Timer configuration unexpectedly.

• Real Time Clock – RTC

  ▆ 32-bit up-counter with a programmable prescaler

  ▆ Alarm function

  ▆ Interrupt and Wake-up event

  The Real Time Clock, RTC for short, includes an APB interface, a 32-bit count-up counter, a  control register, a prescaler, a compare register and a status register. Most of the RTC circuits are  located in the Backup Domain except for the APB interface. The APB interface is located in the  VDD15 power domain. Therefore, it is necessary to be isolated from the ISO signal that comes from  the power control unit when the VDD15 power domain is powered off, that is when the device enters  the Power-Down mode. The RTC counter is used as a wakeup timer to generate a system resume  signal from the Power-Down mode.

• Inter-integrated Circuit – I2 C

  ▆ Supports both master and slave modes with a frequency of up to 1 MHz

  ▆ Provide an arbitration function and clock synchronization

  ▆ Supports 7-bit and 10-bit addressing modes and general call addressing

  ▆ Supports slave multi-addressing mode with maskable address

  The I2 C Module is an internal circuit allowing communication with an external I2 C interface which  is an industry standard two line serial interface used for connection to external hardware. These  two serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I2 C module  provides three data transfer rates: (1) 100 kHz in the Standard mode, (2) 400 kHz in the Fast mode  and (3) 1 MHz in the Fast mode plus mode. The SCL period generation register is used to setup  different kinds of duty cycle implementations for the SCL pulse.

  The SDA line which is connected directly to the I2 C bus is a bi-directional data line between the  master and slave devices and is used for data transmission and reception. The I2 C module also has  an arbitration detect function and clock synchronization to prevent situations where more than one  master attempts to transmit data to the I2 C bus at the same time.

• Serial Peripheral Interface – SPI

  ▆ Supports both master and slave mode

  ▆ Frequency of up to (fPCLK/2) MHz for master mode and (fPCLK/3) MHz for slave mode

  ▆ FIFO Depth: 8 levels

  ▆ Multi-master and multi-slave operation

  The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function  in both master and slave mode. The SPI interface uses 4 pins, which are the serial data input and  output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device  acts as a master device which controls the data flow using the SEL and SCK signals to indicate the  start of data communication and the data sampling rate. To receive a data byte, the streamed data  bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data  transmission is carried out in a similar way but in a reverse sequence. The mode fault detection  provides a capability for multi-master applications.

• Universal Synchronous Asynchronous Receiver Transmitter – USART

  ▆ Supports both asynchronous and clocked synchronous serial communication modes

  ▆ Asynchronous operating baud rate up to (fPCLK/16) MHz and synchronous operating rate up to  (fPCLK/8) MHz

  ▆ Full duplex communication

  ▆ Fully programmable serial communication characteristics including:

  ● Word length: 7, 8, or 9-bit character

  ● Parity: Even, odd, or no-parity bit generation and detection

  ● Stop bit: 1 or 2 stop bit generation

  ● Bit order: LSB-first or MSB-first transfer

  ▆ Error detection: Parity, overrun and frame error

  ▆ Auto hardware flow control mode – RTS, CTS

  ▆ IrDA SIR encoder and decoder

  ▆ RS485 mode with output enable control

  ▆ FIFO Depth: 8-Level for both receiver and transmitter

  The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible  full duplex data exchange using synchronous or asynchronous transfer. The USART is used to  translate data between parallel and serial interfaces, and is commonly used for RS232 standard  communication. The USART peripheral function supports four types of interrupt including Line  Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt  and Time Out Interrupt. The USART module includes a transmitter FIFO, (TX_FIFO) and a  receiver FIFO (RX_FIFO). The software can detect a USART error status by reading the Line  Status Register, LSR. The status includes the type and the condition of transfer operations as well  as several error conditions resulting from Parity, Overrun, Framing and Break events.

• Universal Asynchronous Receiver Transmitter – UART

  ▆ Asynchronous serial communication operating baud-rate up to (fPCLK/16) MHz

  ▆ Full duplex communication

  ▆ Fully programmable serial communication characteristics including:

  ● Word length: 7, 8 or 9-bit character

  ● Parity: Even, odd or no-parity bit generation and detection

  ● Stop bit: 1 or 2 stop bit generation

  ● Bit order: LSB-first or MSB-first transfer

  ▆ Error detection: Parity, overrun and frame error

  The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data  exchange using asynchronous transfer. The UART is used to translate data between parallel and  serial interfaces, and is commonly used for RS232 standard communication. The UART peripheral  function supports Line Status Interrupt. The software can detect a UART error status by reading  the Line Status Register, LSR. The status includes the type and the condition of transfer operations  as well as several error conditions resulting from Parity, Overrun, Framing and Break events.

• Smart Card Interface – SCI

  ▆ Supports ISO 7816-3 standard

  ▆ Character mode

  ▆ Single transmit buffer and single receive buffer

  ▆ 11-bit ETU (elementary time unit) counter

  ▆ 9-bit guard time counter

  ▆ 24-bit general purpose waiting time counter

  ▆ Parity generation and checking

  ▆ Automatic character retry on parity error detection in transmission and reception modes

  The Smart Card Interface is compatible with the ISO 7816-3 standard. This interface includes  Card Insertion/Removal detection, SCI data transfer control logic and data buffers, internal  Timer Counters and corresponding control logic circuits to perform all the necessary Smart Card  operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication  with the external Smart Card. The overall functions of the Smart Card interface are controlled  by a series of registers including control and status registers together with several corresponding  interrupts which are generated to get the attention of the microcontroller for SCI transfer status.

• Inter-IC Sound – I2 S

  ▆ Master or slave mode

  ▆ Mono and stereo

  ▆ I2S-justified, Left-justified, and Right-justified mode

  ▆ 8/16/24/32-bit sample size with 32-bit channel extended

  ▆ 8 × 32-bit Tx & Rx FIFO with PDMA supported

  ▆ 8-bit Fractional Clock Divider with rate control

  The I2 S is a synchronous communication interface that can be used as a master or slave to  exchange data with other audio peripherals, such as ADCs or DACs. The I2 S supports a variety of  data formats. In addition to the stereo I2S-justified, Left-justified and Right-justified modes, there  are mono PCM modes with 8/16/24/32-bit sample size. When the I2 S operates in the master mode,  then when using the fractional divider, it can provide an accurate sampling frequency output and  support the rate control function and fine-tuning of the output frequency to avoid system problems  caused by the cumulative frequency error between different devices.

• Cyclic Redundancy Check – CRC

  ▆ Supports CRC16 polynomial: 0x8005, X16+X15+X2 +1

  ▆ Supports CCITT CRC16 polynomial: 0x1021, X16+X12+X5 +1

  ▆ Supports IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X32+X26+X23+X22+X16+X12+X11+X10+X8 +X7 +X5 +X4 +X2 +X+1

  ▆ Supports 1's complement, byte reverse & bit reverse operation on data and checksum

  ▆ Supports byte, half-word & word data size

  ▆ Programmable CRC initial seed value

  ▆ CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit  data

  ▆ Supports PDMA to complete a CRC computation of a block of memory

  The CRC calculation unit is an error detection technique test algorithm which is used to verify data  transmission or storage data correctness. A CRC calculation takes a data stream or a block of data  as input and generates a 16-bit or 32-bit output remainder. Ordinarily, a data stream is suffixed by  a CRC code and used as a checksum when being sent or stored. Therefore, the received or restored  data stream is calculated by the same generator polynomial as described above. If the new CRC  code result does not match the one calculated earlier, that means data stream contains a data error.

• Peripheral Direct Memory Access – PDMA

  ▆ 12 channels with trigger source grouping

  ▆ 8/16/32-bit width data transfer

  ▆ Supports Address increment, decrement or fixed mode

  ▆ 4-level programmable channel priority

  ▆ Auto reload mode

  ▆ Supports trigger source: ADC, SPI, EBI, CRC, USART, UART, I2 C, I2 S, GPTM, MCTM, SCI, AES, SDIO and software  request

  The Peripheral Direct Memory Access controller, PDMA, moves data between the peripherals  and the system memory on the AHB bus. Each PDMA channel has a source address, destination  address, block length and transfer count. The PDMA can exclude the CPU intervention and avoid  interrupt service routine execution. It improves system performance as the software does not need  to join each data movement operation.

• External Bus Interface – EBI

  ▆ Programmable interface for various memory types

  ▆ Translate the AHB transactions into the appropriate external device protocol

  ▆ Memory bank regions and independent chip select control for each memory bank

  ▆ Programmable timings to support a wide range of devices

  ▆ Includes page read mode

  ▆ Automatic translation when the AHB transaction width and external memory interface width is  different

  ▆ Write buffer to decrease the stalling of the AHB write burst transaction

  ▆ Multiplexed and non-multiplexed address and data line configurations

  ● Up to 25 address lines

  ● Up to 16-bit data bus width

  The external bus interface is able to access external parallel interface devices such as SRAM,  Flash and LCD modules. The interface is memory mapped into the internal address map of the CPU. The data and address lines are multiplexed in order to reduce the number of pins required to  connect to the external devices. The read/write timing of the bus can be adjusted to meet the timing  specification of the external devices. Note the interface only supports asynchronous 8-bit or 16-bit  bus interface.

• Universal Serial Bus Device Controller – USB

  ▆ Complies with USB 2.0 full-speed (12 Mbps) specification

  ▆ On-chip USB full-speed transceiver

  ▆ 1 control endpoint (EP0) for control transfer

  ▆ 3 single-buffered endpoints for bulk and interrupt transfer

  ▆ 4 double-buffered endpoints for bulk, interrupt and isochronous transfer

  ▆ 1024 bytes EP-SRAM used as the endpoint data buffers

  The USB device controller is compliant with the USB 2.0 full-speed specification. There is one  control endpoint known as Endpoint 0 and seven configurable endpoints. A 1024 bytes SRAM  is used as the endpoint buffer. Each endpoint buffer size is programmable using corresponding  registers, which provides maximum flexibility for various applications. The integrated USB fullspeed transceiver helps to minimize the overall system complexity and cost. The USB functional  block also contains the resume and suspend feature to meet the requirements of low-power  consumption.

• Advanced Encryption Standard – AES

  ▆ Supports AES Encrypt / Decrypt Function

  ▆ Supports AES ECB/CBC/CTR mode

  ▆ Supports Key Size 128, 192 and 256 bits

  ▆ Supports 4 words Initial Vector for CBC and CTR mode

  ▆ 8 × 32 bits ( Each IN and OUT FIFO Capacity ) for 2 AES Data blocks

  ▆ Supports DMA Interface

  ▆ Supports Word Data Swap Function

  The AES core supports encryption and decryption function. AES only supports 128 bits input data  to do encryption or decryption. Hardware does not pad any bits of input data. Software need to do  pad action at first.

• Secure Digital Input Output – SDIO

  ▆ Supports two different data bus modes: 1-bit (default) and 4-bit

  ▆ Supports two different speed modes: Normal speed (default) and High speed

  ▆ SD clock frequency of up to 48 MHz

  ▆ SPI mode and MMC stream mode not supported

  The SDIO includes a command register, argument register, response registers, data buffer, timeout  counter and error detection logic. The SDIO supports single block and multi-block data transfers  and is compatible with the PDMA, minimizing processor intervention for large data transfers.

• CMOS Sensor Interface – CSIF (HT32F22366 only)

  ▆ Up to 2048 × 2048 input resolution

  ▆ Supports 8-bit YUV422 and Raw RGB formats

  ▆ Up to (fHCLK/3) MHz input pixel clock frequency

  ▆ Multi VSYNC and HSYNC settings for image capture

  ▆ Hardware window capture function

  ▆ Fractional hardware sub-sample function

  ▆ Dual FIFOs each with a capacity of 8 × 32 bits which can be read by the PDMA or CPU

  The CMOS Sensor Interface, otherwise known as the CSIF, provides an interface for image  capture from CMOS sensors. The device can be connected to the CMOS sensor directly using its  CMOS Sensor Interface. The CSIF supports both Vertical SYNC and Horizontal SYNC modes for  image capture implementation. The CSIF consists of window capture and sub-sampling functions  together with dual FIFOs, each with a capacity of 8 × 32 bits, to store data which can be moved  to the internal SRAM via the Peripheral Direct Memory Access circuitry, PDMA. The CSIF does  not support image data conversion or decode but rather transfers the image data received from the  CMOS sensor to the internal SRAM transparently.

• Debug Support

  ▆ Serial Wire or JTAG Debug Port SWJ-DP

  ▆ 6 instruction comparators and 2 literal comparators for hardware breakpoint or code / literal  patches

  ▆ 4 comparators for hardware watchpoints

  ▆ 1-bit asynchronous trace for serial wire debug mode – TRACESWO

• Package and Operation Temperature

  ▆ 46-pin QFN, 48/64/100-pin LQFP package

  ▆ Operation temperature range: -40 °C to 85 °C