Product Features

• Core

  ▆ 32-bit Arm® Cortex®-M0+ processor core

  ▆ Up to 40 MHz operating frequency

  ▆ 0.93 DMIPS/MHz – Dhrystone v2.1

  ▆ Single-cycle multiplication

  ▆ Integrated Nested Vectored Interrupt Controller (NVIC)

  ▆ 24-bit SysTick timer

  The Cortex®-M0+ processor is a very low gate count, highly energy efficient processor that is  intended for microcontroller and deeply embedded applications that require an area optimized,  low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb® instruction sets, single-cycle I/O ports, hardware multiplier and low latency interrupt respond time.

• On-chip Memory

  ▆ Up to 64 KB on-chip Flash memory for instruction/data and options storage

  ▆ Up to 8 KB on-chip SRAM

  ▆ Supports multiple booting modes

  The Arm® Cortex®-M0+ processor accesses and debug accesses share the single external interface  to external AHB peripherals. The processor accesses take priority over debug accesses. The  maximum address range of the Cortex®-M0+ is 4 GB since it has a 32-bit bus address width.  Additionally, a pre-defined memory map is provided by the Cortex®-M0+ processor to reduce  the software complexity of repeated implementation by different device vendors. However, some  regions are used by the Arm® Cortex®-M0+ system peripherals. Refer to the Arm® Cortex®-M0+  Technical Reference Manual for more information. Figure 2 in the Overview chapter shows the  memory map of the device, including code, SRAM, peripheral and other pre-defined regions.

• Bluetooth Low Energy Controller – BLEC

  ▆ 2.4 GHz RF transceiver compatible with Bluetooth Low Energy (BLE) 5.2 specification

  ▆ 16 MHz external crystal reference clock

  ▆ GFSK modulation, Frequency-Hopping Spread Spectrum (FHSS)

  ▆ Support LE 1 Mbps, 2 Mbps

  ▆ Receiver supports programmable gain control of over 70 dB

  ▆ Excellent receiver sensitivity of -94 dBm @ 1 Mbps

  ▆ Programmable transmitter output power up to +3.5 dBm

  ▆ Software-based True Random Number Generator (TRNG)

  ▆ Three operating modes: Normal, Deep-Sleep and Power-Down

  The Bluetooth Low Energy Controller, BLEC, is an ultra-low power 2.4 GHz RF transceiver  compatible with the BLE 5.2 specification. With excellent receiver sensitivity and very low active RF current consumption, the device provides an excellent battery lifetime. The BLEC includes the  RF transceiver, modem, protocol processing logic, link layer controller and link layer firmware  library which support for Bluetooth 5.2 LE 1 Mbps and LE 2 Mbps connections. For power saving,  the BLEC supports Deep-Sleep and Power-Down modes, which can be combined with the PWRCU  (Power Management Control Unit) Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down operating  modes to reduce power consumption for BLE applications.

• Flash Memory Controller – FMC

  ▆ Flash accelerator for maximum efficiency

  ▆ 32-bit word programming with In System Programming Interface (ISP) and In Application  Programming (IAP)

  ▆ Flash protection capability to prevent illegal access

  The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer for  the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower than  the CPU, a wide access interface with a pre-fetch buffer is provided for the Flash Memory in order  to reduce the CPU waiting time which will cause CPU instruction execution delays. Flash Memory  word program/page erase functions are also provided.

• Reset Control Unit – RSTCU

  ▆ Supply supervisor:

  ● Power On Reset / Power Down Reset – POR/PDR

  ● Brown Out Detector – BOD

  ● Programmable Low Voltage Detector – LVD

  The Reset Control Unit, RSTCU, has three kinds of reset, a power on reset, a system reset and an  APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.  A system reset resets the processor core and peripheral IP components with the exception of the  SW-DP controller. The resets can be triggered by external signals, internal events and the reset  generators.

• Clock Control Unit – CKCU

  ▆ External 4 to 16 MHz crystal oscillator

  ▆ External 32,768 Hz crystal oscillator

  ▆ Internal 8 MHz RC oscillator trimmed to ±2 % accuracy at 3.3 V operating voltage and 25 °C  operating temperature

  ▆ Internal 32 kHz RC oscillator

  ▆ Integrated system clock PLL

  ▆ Independent clock divider and gating bits for peripheral clock sources

  The Clock Control Unit, CKCU, provides a range of oscillators and clock functions. These include  a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low  Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase Lock Loop (PLL), an HSE clock monitor, clock pre-scalers, clock multiplexers, APB clock divider and  gating circuitry. The clocks of the AHB, APB and Cortex®-M0+ are derived from the system clock  (CK_SYS) which can source from the HSI, HSE, LSI, LSE or system PLL. The Watchdog Timer  and Real Time Clock (RTC) use either the LSI or LSE as their clock source.

• Power Management Control Unit – PWRCU

  ▆ Single VDD power supply: 2.0 V to 3.6 V

  ▆ Integrated 1.5 V regulator for CPU core, peripherals and memories power supply

  ▆ VDD power supply for RTC

  ▆ Two power domains: VDD, 1.5 V

  ▆ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down

  Power consumption can be regarded as one of the most important issues for many embedded  system applications. Accordingly the Power Control Unit, PWRCU, in the device provides many  types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes.  These operating modes reduce the power consumption and allow the application to achieve the best  trade-off between the conflicting demands of CPU operating time, speed and power consumption.

• External Interrupt/Event Controller – EXTI

  ▆ Up to 16 EXTI lines with configurable trigger sources and types

  ▆ All GPIO pins can be selected as EXTI trigger source

  ▆ Source trigger type includes high level, low level, negative edge, positive edge or both edges

  ▆ Individual interrupt enable, wake-up enable and status bits for each EXTI line

  ▆ Software interrupt trigger mode for each EXTI line

  ▆ Integrated deglitch filter for short pulse blocking

  The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate  a wake-up event or interrupt requests independently. Each EXTI line can also be masked  independently

• Analog to Digital Converter – ADC

  ▆ 12-bit SAR ADC engine

  ▆ Up to 1 Msps conversion rate

  ▆ Up to 6 external analog input channels

  A 12-bit multi-channel Analog to Digital Converter is integrated in the device. There are  multiplexed channels, which include up to 6 external analog signal channels and 2 internal  channels. If the input voltage is required to remain within a specific threshold window, an Analog  Watchdog function will monitor and detect these signals. An interrupt will then be generated to  inform the device that the input voltage is not within the preset threshold levels. There are three  conversion modes to convert an analog signal to digital data. The A/D Conversion can be operated  in one shot, continuous and discontinuous conversion modes.

• I/O Ports – GPIO

  ▆ Up to 25 GPIOs

  ▆ Port A, B, C are mapped as 16 external interrupts – EXTI

  ▆ Almost all I/O pins have a configurable output driving current

  There are up to 25 General Purpose I/O pins, GPIO, for the implementation of logic input/output  functions. Each of the GPIO ports has a series of related control and configuration registers to  maximize flexibility and to meet the requirements of a wide range of applications.

  The GPIO ports are pin-shared with other alternative functions to obtain maximum functional  flexibility on the package pins. The GPIO pins can be used as alternative functional pins by  configuring the corresponding registers regardless of the input or output pins. The external  interrupts on the GPIO pins of the device have related control and configuration registers in the  External Interrupt Control Unit, EXTI.

• Motor Control Timer – MCTM

  ▆ 16-bit up/down auto-reload counter

  ▆ 16-bit programmable prescaler allowing counter clock frequency division by any factor between  1 and 65536

  ▆ Input Capture function

  ▆ Compare Match Output

  ▆ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

  ▆ Single Pulse Mode Output

  ▆ Complementary Outputs with programmable dead-time insertion

  ▆ Supports 3-phase motor control and hall sensor interface

  ▆ Break input to force the timer's output signals into a reset or fixed condition

  The Motor Control Timer consists of one 16-bit up/down counter; four 16-bit Capture/Compare  Registers (CCRs), one 16-bit Counter Reload Register (CRR), one 8-bit repetition counter and  several control/status registers. It can be used for a variety of purposes including measuring the  pulse widths of input signals or generating output waveforms such as compare match outputs,  PWM outputs or complementary PWM outputs with dead-time insertion. The MCTM is capable of  offering full functional support for motor control, hall sensor interfacing and brake input.

• General-Purpose Timer – GPTM

  ▆ 16-bit up/down auto-reload counter

  ▆ Up to 4 independent channels for each timer

  ▆ 16-bit programmable prescaler allowing counter clock frequency division by any factor between  1 and 65536

  ▆ Input Capture function

  ▆ Compare Match Output

  ▆ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

  ▆ Single Pulse Mode Output

  ▆ Encoder interface controller with two inputs using quadrature decoder

  The General Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare  Registers (CCRs), one 16-bit Counter Reload Register (CRR) and several control/status registers.  They can be used for a variety of purposes including general time measurement, input signal pulse  width measurement, output waveform generation such as single pulse generation or PWM output  generation. The GPTM supports an Encoder Interface using a decoder with two inputs.

• Single-Channel Timers – SCTM

  ▆ 16-bit up auto-reload counter

  ▆ One channel for each timer

  ▆ 16-bit programmable prescaler that allows division of the counter clock frequency by any factor  between 1 and 65536

  ▆ Input Capture function

  ▆ Compare Match Output

  ▆ PWM waveform generation with Edge-aligned

  The Single Channel Timer Module, SCTM, consists of one 16-bit up-counter, one 16-bit Capture/ Compare Register (CCR), one 16-bit Counter Reload Register (CRR) and several control/status  registers. It can be used for a variety of purposes including general timer, input signal pulse width  measurement or output waveform generation such as PWM output.

• Basic Function Timers – BFTM

  ▆ 32-bit compare match count-up counter – no I/O control features

  ▆ One shot mode – counting stops after a match condition

  ▆ Repetitive mode – restarts counter after a match condition

  The Basic Function Timer is a simple count-up 32-bit counter designed to measure time intervals  and generate a one shot or repetitive interrupts. The BFTM operates in two functional modes,  repetitive or one shot mode. In the repetitive mode the BFTM restarts the counter when a compare  match event occurs. The BFTM also supports a one shot mode which forces the counter to stop  counting when a compare match event occurs.

• Watchdog Timer – WDT

  ▆ 12-bit count-down counter with 3-bit prescaler

  ▆ Reset event for the system

  ▆ Programmable watchdog timer window function

  ▆ Register write protection function

  The Watchdog Timer is a hardware timing circuit that can be used to detect system failures due  to software malfunctions. It includes a 12-bit count-down counter, a prescaler, a WDT delta value  register, a WDT operation control circuitry and a WDT protection mechanism. If the software does  not reload the counter value before a Watchdog Timer underflow occurs, a reset will be generated when the counter underflows. In addition, a reset is also generated if the software reloads the  counter when the counter value is greater than the WDT delta value. This means the counter must  be reloaded within a limited timing window using a specific method. The Watchdog Timer counter  can be stopped while the processor is in the debug mode. There is a register write protect function  which can be enabled to prevent it from changing the Watchdog Timer configuration unexpectedly.

• Real Time Clock – RTC

  ▆ 24-bit count-up counter with a programmable prescaler

  ▆ Alarm function

  ▆ Interrupt and Wake-up event

  The Real Time Clock, RTC, includes an APB interface, a 24-bit count-up counter, a control  register, a prescaler, a compare register and a status register. Most of the RTC circuits are located  in the VDD power domain except for the APB interface. The APB interface is located in the VDD15 power domain. Therefore, it is necessary to be isolated from the ISO signal that comes from the  power control unit when the VDD15 power domain is powered off, that is when the device enters  the Power-Down mode. The RTC counter is used as a wake-up timer to generate a system resume  signal from the Power-Down mode.

• Inter-Integrated Circuit – I2 C

  ▆ Supports both master and slave modes with a frequency of up to 1 MHz

  ▆ Provides an arbitration function and clock synchronization

  ▆ Supports 7-bit and 10-bit addressing modes and general call addressing

  ▆ Supports slave multi-addressing mode using address mask function The I2 C is an internal circuit allowing communication with an external I2 C interface which is an  industry standard two-line serial interface used for connection to external hardware. These two  serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I2 C module  provides three data transfer rates: (1) 100 kHz in the Standard mode, (2) 400 kHz in the Fast mode  and (3) 1 MHz in the Fast plus mode. The SCL period generation register is used to setup different  kinds of duty cycle implementations for the SCL pulse.

  The SDA line which is connected directly to the I2 C bus is a bi-directional data line between the  master and slave devices and is used for data transmission and reception. The I2 C also has an  arbitration detection and clock synchronization function to prevent situations where more than one  master attempts to transmit data to the I2 C bus at the same time.

• Serial Peripheral Interface – SPI

  ▆ Supports both master and slave modes

  ▆ Frequency of up to (fPCLK/2) MHz for the master mode and (fPCLK/3) MHz for the slave mode

  ▆ FIFO Depth: 8 levels

  ▆ Multi-master and multi-slave operation

  The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function  in both master and slave modes. The SPI interface uses 4 pins, which are the serial data input and  output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device  acts as a master device which controls the data flow using the SEL and SCK signals to indicate the  start of data communication and the data sampling rate. To receive a data byte, the streamed data  bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data  transmission is carried out in a similar way but in a reverse sequence. The mode fault detection  provides a capability for multi-master applications.

• Universal Synchronous Asynchronous Receiver Transmitter – USART

  ▆ Supports both asynchronous and clocked synchronous serial communication modes

  ▆ Asynchronous operating baud rate up to (fPCLK/16) MHz and synchronous operating rate up to  (fPCLK/8) MHz

  ▆ Full duplex communication

  ▆ Fully programmable serial communication characteristics including:

  ● Word length: 7, 8 or 9-bit character

  ● Parity: Even, odd, or no-parity bit generation and detection

  ● Stop bit: 1 or 2 stop bit generation

  ● Bit order: LSB-first or MSB-first transfer

  ▆ Error detection: Parity, overrun and frame error

  ▆ Auto hardware flow control mode – RTS, CTS

  ▆ IrDA SIR encoder and decoder

  ▆ RS485 mode with output enable control

  ▆ FIFO Depth: 8-level for both receiver and transmitter

  The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full  duplex data exchange using synchronous or asynchronous data transfer. The USART is used to  translate data between parallel and serial interfaces, and is commonly used for RS232 standard  communication. The USART peripheral function supports four types of interrupt including Line  Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt  and Time Out Interrupt. The USART module includes a transmitter FIFO, TX FIFO, and receiver  FIFO, RX FIFO. The software can detect a USART error status by reading the Line Status  Register, LSR. The status includes the type and the condition of transfer operations as well as  several error conditions resulting from Parity, Overrun, Framing and Break events.

• Universal Asynchronous Receiver Transmitter – UART

  ▆ Asynchronous serial communication operating baud-rate up to fPCLK/16 MHz

  ▆ Full duplex communication

  ▆ Fully programmable serial communication characteristics including:

  ● Word length: 7, 8 or 9-bit character

  ● Parity: Even, odd or no-parity bit generation and detection

  ● Stop bit: 1 or 2 stop bit generation

  ● Bit order: LSB-first or MSB-first transfer

  ▆ Error detection: Parity, overrun and frame error

  The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data  exchange using asynchronous transfer. The UART is used to translate data between parallel and  serial interfaces, and is commonly used for RS232 standard communication. The UART peripheral  function supports Line Status Interrupt. The software can detect a UART error status by reading  the Line Status Register, LSR. The status includes the type and the condition of transfer operations  as well as several error conditions resulting from Parity, Overrun, Framing and Break events.

• Cyclic Redundancy Check – CRC

  ▆ Supports CRC16 polynomial: 0x8005, X16 + X15 + X2  + 1

  ▆ Supports CCITT CRC16 polynomial: 0x1021, X16 + X12 + X5  + 1

  ▆ Supports IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8  + X7  + X5  + X4  + X2  + X + 1

  ▆ Supports 1's complement, byte reverse & bit reverse operation on data and checksum

  ▆ Supports byte, half-word & word data size

  ▆ Programmable CRC initial seed value

  ▆ CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit  data

  The CRC calculation unit is an error detection technique test algorithm and is used to verify data  transmission or storage data correctness. A CRC calculation takes a data stream or a block of data  as its input and generates a 16-bit or 32-bit output remainder. Ordinarily, a data stream is suffixed  by a CRC code and used as a checksum when being sent or stored. Therefore, the received or  restored data stream is calculated by the same generator polynomial as described above. If the new  CRC code result does not match the one calculated earlier, that means the data stream contains a  data error.

• Debug Support

  ▆ Serial Wire Debug Port – SW-DP

  ▆ 4 comparators for hardware breakpoints or code / literal patches

  ▆ 2 comparators for hardware watch points

• Package and Operation Temperature

  ▆ 46-pin QFN package

  ▆ Operation temperature range: -40 °C to +85 °C