Product Features

• Core

  ▆32-bit Arm® Cortex®-M0+ processor core

  ▆Up to 60 MHz operating frequency

  ▆Single-cycle multiplication

  ▆Integrated Nested Vectored Interrupt Controller (NVIC)

  ▆24-bit SysTick timer

  The Cortex®-M0+ processor is a very low gate count, highly energy efficient processor that is  intended for microcontroller and deeply embedded applications that require an area optimized,  low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb® instruction sets, single-cycle I/O ports, hardware multiplier and low latency interrupt respond time.

• On-chip Memory

  ▆Up to 128 KB on-chip Flash memory for instruction/data and option storage

  ▆Up to 16 KB on-chip SRAM

  ▆Supports multiple booting modes

  The Arm® Cortex®-M0+ processor access and debug access share the single external interface to  external AHB peripherals. The processor access takes priority over debug access. The maximum  address range of the Cortex®-M0+ is 4 GB since it has a 32-bit bus address width. Additionally,  a pre-defined memory map is provided by the Cortex®-M0+ processor to reduce the software  complexity of repeated implementation by different device vendors. However, some regions are  used by the Arm® Cortex®-M0+ system peripherals. Refer to the Arm® Cortex®-M0+ Technical  Reference Manual for more information. Figure 2 in the Overview chapter shows the memory map  of the HT32F5828 device, including code, SRAM, peripheral and other pre-defined regions.

• Flash Memory Controller – FMC

  ▆32-bit word programming with In System Programming Interface (ISP) and In Application  Programming (IAP)

  ▆Flash protection capability to prevent illegal access

  The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer for  the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower than  the CPU, a wide access interface with a pre-fetch buffer is provided for the Flash Memory in order  to reduce the CPU waiting time which will cause CPU instruction execution delays. Flash Memory  word programming/page erase functions are also provided.

• Reset Control Unit – RSTCU

  ▆Supply supervisor

  ● Power on Reset / Power down Reset – POR / PDR

  ● Brown-out Detector – BOD

  ● Programmable Low Voltage Detector – LVD

  The Reset Control Unit, RSTCU, has three kinds of reset, a power on reset, a system reset and an  APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.  A system reset resets the processor core and peripheral IP components with the exception of the  SW-DP controller. The resets can be triggered by external signals, internal events and the reset  generators.

• Clock Control Unit – CKCU

  ▆External 4 to 16 MHz crystal oscillator

  ▆External 32.768 kHz crystal oscillator

  ▆Internal 8 MHz RC oscillator trimmed to ±2 % accuracy at 3.3 V operating voltage and 25 °C  operating temperature

  ▆Internal 32 kHz RC oscillator

  ▆Integrated clock PLL and USB PLL

  ▆Independent clock divider and gating bits for peripheral clock sources

  The Clock Control Unit, CKCU, provides a range of oscillators and clock functions. These include  a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low  Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase Lock  Loop (PLL), an HSE clock monitor, clock pre-scalers, clock multiplexers, APB clock divider and  gating circuitry. The clocks of the AHB, APB and Cortex®-M0+ are derived from the system clock  (CK_SYS) which can source from the HSI, HSE, LSI, LSE or system PLL. The Watchdog Timer  and Real Time Clock (RTC) use either the LSI or LSE as their clock source.

• Power Management Control Unit – PWRCU

  ▆Single VDD power supply: 1.65 V to 3.6 V

  ▆Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply

  ▆VDD power supply for RTC

  ▆Two power domains: VDD and 1.5 V power domains

  ▆Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes

  Power consumption can be regarded as one of the most important issues for many embedded system  applications. Accordingly the Power Control Unit, PWRCU, in the device provides many types of  power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes. These operating modes reduce the power consumption and allow the application to achieve the best trade-off  between the conflicting demands of CPU operating time, speed and power consumption.

• External Interrupt/Event Controller – EXTI

  ▆Up to 16 EXTI lines with configurable trigger sources and types

  ▆All GPIO pins can be selected as EXTI trigger source

  ▆Source trigger type includes high level, low level, negative edge, positive edge or both edges

  ▆Individual interrupt enable, wakeup enable and status bits for each EXTI line

  ▆Software interrupt trigger mode for each EXTI line

  ▆Integrated deglitch filter for short pulse blocking

  The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate a  wake-up event or interrupt requests independently. Each EXTI line can also be masked independently

• I/O Ports – GPIO

  ▆Up to 67 GPIOs

  ▆Port A, B, C, D, E are mapped as 16 external interrupts – EXTI

  ▆Almost all I/O pins have configurable output driving current

  There are up to 67 General Purpose I/O pins, GPIO, for the implementation of logic input/output  functions. Each of the GPIO ports has a series of related control and configuration registers to  maximize flexibility and to meet the requirements of a wide range of applications.

  The GPIO ports are pin-shared with other alternative functions to obtain maximum functional  flexibility on the package pins. The GPIO pins can be used as alternative functional pins by  configuring the corresponding registers regardless of the input or output pins. The external  interrupts on the GPIO pins of the device have related control and configuration registers in the  External Interrupt Control Unit, EXTI.

• Universal Serial Bus Device Controller – USB

  ▆Complies with USB 2.0 Full-Speed (12 Mbps) specification

  ▆Fully integrated USB full-speed transceiver

  ▆1 control endpoint (EP0) for control transfer

  ▆3 single-buffered endpoints for bulk and interrupt transfer

  ▆4 double-buffered endpoints for bulk, interrupt and isochronous transfer

  ▆1,024 bytes EP_SRAM used as the endpoint data buffers

  The USB device controller is compliant with the USB 2.0 full-speed specification. There is one  control endpoint known as Endpoint 0 and seven configurable endpoints. A 1024-byte SRAM  is used as the endpoint buffers. Each endpoint buffer size is programmable using corresponding  registers, thus providing maximum flexibility for various applications. The integrated USB full-speed  transceiver helps to minimize overall system complexity and cost. The USB also contains suspend  and resume features to meet low-power consumption requirement.

• Inter-integrated Circuit – I2 C

  ▆Supports both master and slave modes with a frequency of up to 1 MHz

  ▆Provides an arbitration function and clock synchronization

  ▆Supports 7-bit and 10-bit addressing modes and general call addressing

  ▆Supports slave multi-addressing mode using address mask function

  The I2 C is an internal circuit allowing communication with an external I2 C interface which is an  industry standard two line serial interface used for connection to external hardware. These two  serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I2 C module  provides three data transfer rates: 100 kHz in the Standard mode, 400 kHz in the Fast mode and 1 MHz in the Fast plus mode. The SCL period generation register is used to setup different kinds of  duty cycle implementation for the SCL pulse.

  The SDA line which is connected directly to the I2 C bus is a bidirectional data line between the  master and slave devices and is used for data transmission and reception. The I2 C also has an  arbitration detection and clock synchronization function to prevent the situations where more than  one master attempts to transmit data to the I2 C bus at the same time.

• Serial Peripheral Interface – SPI

  ▆Supports both master and slave modes

  ▆Frequency of up to (fPCLK/2) MHz for the master mode and (fPCLK/3) MHz for the slave mode

  ▆FIFO Depth: 8 levels

  ▆Multi-master and multi-slave operation

  The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function  in both master and slave modes. The SPI interface uses 4 pins, among which are serial data input  and output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI  device acts as a master who controls the data flow using the SEL and SCK signals to indicate the  start of the data communication and the data sampling rate. To receive a data byte, the streamed  data bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data  transmission is carried out in a similar way but with the reverse sequence. The mode fault detection  provides a capability for multi-master applications.

• Universal Synchronous Asynchronous Receiver Transmitter – USART

  ▆Supports both asynchronous and clocked synchronous serial communication modes

  ▆Programming baud rate clock frequency up to (fPCLK/16) MHz for Asynchronous mode and (fPCLK/8) MHz for synchronous mode

  ▆Full duplex communication

  ▆Fully programmable serial communication characteristics including

  ● Word length: 7, 8 or 9-bit character

  ● Parity: Even, odd or no-parity bit generation and detection

  ● Stop bit: 1 or 2 stop bits generation

  ● Bit order: LSB-first or MSB-first transfer

  ▆Error detection: Parity, overrun and frame error

  ▆Auto hardware flow control mode – RTS, CTS

  ▆IrDA SIR encoder and decoder

  ▆RS485 mode with output enable control

  ▆FIFO Depth: 8-level for both receiver and transmitter

  The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full  duplex data exchange using synchronous or asynchronous data transfer. The USART is used to  translate data between parallel and serial interfaces, and is commonly used for RS232 standard  communication. The USART peripheral function supports four types of interrupt including Line  Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt and  Time Out Interrupt. The USART module includes a transmitter FIFO, (TX_FIFO) and receiver FIFO  (RX_FIFO). The software can detect a USART error status by reading the USART Status & Interrupt  Flag Register, USRSIFR. The status includes the type and the condition of transfer operations as well  as several error conditions resulting from Parity, Overrun, Framing and Break events.

• Universal Asynchronous Receiver Transmitter – UART

  ▆Asynchronous serial communication operating baud-rate clock frequency up to (fPCLK/16) MHz

  ▆Full duplex communication

  ▆Fully programmable serial communication characteristics including

  ● Word length: 7, 8 or 9-bit character

  ● Parity: Even, odd or no-parity bit generation and detection

  ● Stop bit: 1 or 2 stop bits generation

  ● Bit order: LSB-first or MSB-first transfer

  ▆Error detection: Parity, overrun and frame error

  The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data  exchange using asynchronous transfer. The UART is used to translate data between parallel and  serial interfaces, and is commonly used for RS232 standard communication. The UART peripheral  function supports Line Status Interrupt. The software can detect a UART error status by reading  the UART Status & Interrupt Flag Register, URSIFR. The status includes the type and the  condition of transfer operations as well as several error conditions resulting from Parity, Overrun,  Framing and Break events.

• Smart Card Interface – SCI

  ▆Supports ISO 7816-3 standard

  ▆Character Transfer mode

  ▆Single transmit buffer and single receive buffer

  ▆11-bit ETU (Elementary Time Unit) counter

  ▆9-bit guard time counter

  ▆24-bit general purpose waiting time counter

  ▆Parity generation and check functions

  ▆Automatic character retry on parity error detection in transmission and reception modes

  The Smart Card Interface, SCI, is compatible with the ISO 7816-3 standard. This interface includes  functions for Card Insertion/Removal detection, SCI data transfer control logic and data buffers,  internal Timer Counters and corresponding control logic circuits to perform the required Smart  Card operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication  with the external Smart Card. The overall functions of the Smart Card interface are controlled  by a series of registers including control and status registers together with several corresponding  interrupts which are generated to get the attention of the microcontroller for SCI transfer status.

• Inter-IC Sound – I2 S

  ▆Master or Slave mode

  ▆Mono and Stereo

  ▆I 2 S-justified, Left-justified and Right-justified mode

  ▆8/16/24/32-bit sample size with 32-bit channel extended

  ▆8 × 32-bit TX & RX FIFO with PDMA supported

  ▆8-bit Fractional Clock Divider with rate control

  The I2 S is a synchronous communication interface that can be used as a master or slave to  exchange data with other audio peripherals, such as ADCs or DACs. The I2 S supports a variety of  data formats. In addition to the stereo I2 S-justified, Left-justified and Right-justified modes, there  are mono PCM modes with 8/16/24/32-bit sample size. When the I2 S operates in the master mode,  using the fractional divider, it can provide an accurate sampling frequency output and support the  rate control function and fine-tuning of the output frequency to avoid system problems caused by  the cumulative frequency error between different devices.

• Analog to Digital Converter – ADC

  ▆12-bit SAR ADC engine

  ▆Up to 1 Msps conversion rate

  ▆Up to 10 external analog input channels

  A 12-bit multi-channel Analog to Digital Converter is integrated in the device. There are  multiplexed channels, which include up to 10 external analog signal channels and 4 internal  channels which can be measured. If the input voltage is required to remain within a specific  threshold window, an Analog Watchdog function will monitor and detect these signals. An  interrupt will then be generated to inform that the input voltage is higher or lower than the set  thresholds. There are three conversion modes to convert an analog signal to digital data. The A/D  Conversion can be operated in one shot, continuous and discontinuous conversion modes.

  The internal voltage reference (VREF) which can provide a stable reference voltage for the A/D  Converter and Comparators is internally connected to the ADC input channel. The precise voltage  of the VREF is individually measured for each part by Holtek during production test.

• Comparator – CMP

  ▆Rail-to-rail comparators

  ▆Configurable negative inputs used for flexible voltage selection

  ● External CN pin

  ● Internal 8-bit CVR output

  ▆Programmable hysteresis

  ▆Programming respond speed and consumption

  ▆Comparator output can be routed to I/O pin, to multiple timers or ADC trigger inputs

  ▆8-bit CVR can be configurable to dedicated I/O for voltage reference

  ▆Comparator has interrupt generation capability with wakeup from Sleep, Deep-Sleep1 or Deep-Sleep2 mode through the EXTI controller

  The two general purpose comparators, CMP, are implemented within the device. They can be  configured either as standalone comparators or combined with the different kinds of peripheral IP.  Each comparator is capable of asserting interrupts to the NVIC or waking up the CPU from the  Sleep, Deep-Sleep1 or Deep-Sleep2 mode through the EXTI wakeup event management unit.

• Digital to Analog Converter – DAC

  ▆Two DAC converters with each having one output channel

  ▆12-bit or 8-bit resolution

  ▆Maximum 500 ksps conversion updating rate

  ▆Dual DAC channels for implementing simultaneous conversion

  ▆Supports voltage output buffer mode and bypass voltage output buffer mode

  ▆Reference voltage from internal reference voltage VREF or VDDA

  The DAC Module has two Digital to Analog Converters. Each is a 12-bit, voltage output digital to  analog converter and has one output channel. The DAC can be configured in 8-bit or 12-bit mode.  The DAC conversion could be implemented independently or simultaneously when both channels  are grouped together for synchronous update operation.

• General-Purpose Timer – GPTM

  ▆16-bit up/down auto-reload counter

  ▆Up to 4 independent channels for each timer

  ▆16-bit programmable prescaler that allows division of the counter clock frequency by any factor  between 1 and 65536

  ▆Input Capture function

  ▆Compare Match Output

  ▆PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

  ▆Single Pulse Mode Output

  ▆Encoder interface controller with two inputs using quadrature decoder

  The General-Purpose Timer, consists of one 16-bit up/down-counter, four 16-bit Capture/Compare  Registers (CCRs), one 16-bit Counter Reload Register (CRR) and several control/status registers.

  They can be used for a variety of purposes including general time measurement, input signal pulse  width measurement, output waveform generation such as single pulse generation or PWM output  generation. The GPTM supports an Encoder Interface using a decoder with two inputs.

• Pulse-Width-Modulation Timer – PWM

  ▆16-bit up / down auto-reload counter

  ▆Up to 4 independent channels for each timer

  ▆16-bit programmable prescaler that allows division of the counter clock frequency by any factor  between 1 and 65536

  ▆Compare Match Output

  ▆PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

  ▆Single Pulse Mode Output

  The Pulse-Width-Modulation Timer consists of one 16-bit up/down-counter, four 16-bit Compare  Registers (CRs), one 16-bit Counter Reload Register (CRR) and several control / status registers. It  can be used for a variety of purposes including general timer and output waveform generation such  as single pulse generation or PWM output.

• Single Channel Timer – SCTM

  ▆16-bit auto-reload up-counter

  ▆One channel for each timer

  ▆16-bit programmable prescaler that allows division of the counter clock frequency by any factor  between 1 and 65536

  ▆Input Capture function

  ▆Compare Match Output

  ▆PWM waveform generation with Edge-aligned

  The Single Channel Timer consists of one 16-bit up-counter, one 16-bit Capture/Compare Register  (CCR), one 16-bit Counter Reload Register (CRR) and several control / status registers. It can be  used for a variety of purposes including general timer, input signal pulse width measurement or  output waveform generation such as PWM outputs.

• Basic Function Timer – BFTM

  ▆32-bit compare match up-counter – no I/O control features

  ▆One shot mode – stops counting when compare match occurs

  ▆Repetitive mode – restarts counter when compare match occurs

  The Basic Function Timer is a simple 32-bit up-counting counter designed to measure time  intervals, generate one shots or generate repetitive interrupts. The BFTM can operate in two  functional modes which are repetitive and one shot modes. In the repetitive mode, the counter will  be restarted at each compare match event. The BFTM also supports a one shot mode which will  force the counter to stop counting when a compare match event occurs.

• Watchdog Timer – WDT

  ▆12-bit down-counter with 3-bit prescaler

  ▆Provide reset to the system

  ▆Programmable watchdog timer window function

  ▆Register write protection function

  The Watchdog Timer is a hardware timing circuit that can be used to detect a system lock-up due to  software trapped in a deadlock. It includes a 12-bit down-counter, a prescaler, a WDT delta value  register, WDT operation control circuitry and a WDT protection mechanism. If the software does  not reload the counter value before a Watchdog Timer underflow occurs, a reset will be generated  when the counter underflows. In addition, a reset is also generated if the software reloads the counter  before it reaches a delta value. It means that the counter reload must occur when the Watchdog timer  value has a value within a limited window using a specific method. The Watchdog Timer counter  can be stopped when the processor is in the debug mode. The register write protection function can  be enabled to prevent an unexpected change in the Watchdog timer configuration.

• Real Time Clock – RTC

  ▆24-bit up-counter with a programmable prescaler

  ▆Alarm function

  ▆Interrupt and Wake-up event

  The Real Time Clock, RTC, circuitry includes the APB interface, a 24-bit up-counter, a control  register, a prescaler, a compare register and a status register. Most of the RTC circuits are located  in the VDD power domain except for the APB interface. The APB interface is located in the VDD15 power domain. Therefore, it is necessary to be isolated by the ISO signal that comes from the power  control unit when the VDD15 power domain is powered off, i.e., when the device enters the PowerDown mode. The RTC counter is used as a wakeup timer to generate a system resume or interrupt  signal from the MCU power saving modes.

• Cyclic Redundancy Check – CRC

  ▆Supports CRC16 polynomial: 0x8005, X16 + X15 + X2 + 1

  ▆Supports CCITT CRC16 polynomial: 0x1021, X16 + X12 + X5 + 1

  ▆Supports IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8  + X7  + X5  + X4  + X2  + X + 1

  ▆Supports 1's complement, byte reverse & bit reverse operation on data and checksum

  ▆Supports byte, half-word & word data size

  ▆Programmable CRC initial seed value

  ▆CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit data

  ▆Supports PDMA to complete a CRC computation of a block of memory

  The CRC calculation unit is an error detection technique test algorithm and is used to verify data  transmission or storage data correctness. A CRC calculation takes a data stream or a block of data as its input and generates a 16-bit or 32-bit output remainder. Ordinarily, a data stream is suffixed  by a CRC code and used as a checksum when being sent or stored. Therefore, the received or  restored data stream is calculated by the same generator polynomial as described above. If the new  CRC code result does not match the one calculated earlier, that means the data stream contains a  data error.

• Peripheral Direct Memory Access – PDMA

  ▆6 channels with trigger source grouping

  ▆8-bit, 16-bit and 32-bit width data transfer

  ▆Supports linear address, circular address and fixed address modes

  ▆4-level programmable channel priority

  ▆Auto reload mode

  ▆Supports trigger source: ADC, SPI, USART, UART, SCI, I 2 C, I 2 S, GPTM, PWM, AES-128 and software request

  The Peripheral Direct Memory Access controller, PDMA, moves data between the peripherals  and the system memory on the AHB bus. Each PDMA channel has a source address, destination  address, block length and transfer count. The PDMA can exclude the CPU intervention and avoid  interrupt service routine execution. It improves system performance as the software does not need  to connect each data movement operation.

• Hardware Divider – DIV

  ▆Signed/unsigned 32-bit divider

  ▆Calculate in 8 clock cycles, load in 1 clock cycle

  ▆Division by zero error Flag

  The divider is the truncated division and needs a software triggered start signal by using the control  register "START" bit. After 8 clock cycles, the divider calculate complete flag will be set to 1, and  if the divisor register data is zero, the division by zero error flag will be set to 1

• Liquid Crystal Display Controller – LCD

  ▆LCD Driver function with Static, 1/2, 1/3, 1/4, 1/6 and 1/8 duty

  ▆LCD Driver function with Static, 1/2, 1/3 or 1/4 bias

  ▆Supports R type bias type

  ▆Clock source can be selected from the LSI (32 kHz), LSE (32.768 kHz) or a clock ratio of either  the HSI or HSE

  ▆Contains three embedded LCD bias reference resistor ladders

  ▆Double buffered memory

  ▆Software selectable charge pump voltage

  ▆Programmable dead time between frames – up to 7/2 phase periods for type A waveforms and 7  phase periods for type B waveforms

  ▆Software selectable waveform type: type A or type B waveform

  ▆LCD frame interrupt

  ▆Blink capability: Up to 1, 2, 3, 4, 6, 8 or all pixels which can be programmed to blink

  The LCD controller is a digital controller/driver for monochrome passive liquid crystal displays.  It includes up to 8 common terminals and 37 segment terminals to drive 148 (4 commons × 37  segments) or 264 (8 commons × 33 segments) LCD picture elements (pixels). The exact number  of terminals depends on the device package pin out. An integrated charge pump function can be  enabled to provide the LCD glass with higher voltage than the system voltage.

• Advanced Encryption Standard – AES-128

  ▆Supports AES Encrypt / Decrypt functions

  ▆Supports AES ECB/CBC/CTR modes

  ▆Supports Key Size of 128 bits

  ▆Supports 4 words Initial Vector for CBC and CTR modes

  ▆4 × 32 bits AES data buffer

  ▆Supports PDMA interface

  ▆Supports Word Data Swap function

  The AES core supports both encryption and decryption functions and supports 128-bit input data.  It should be noted that hardware does not pad out any input data bits, therefore users need to do pad  action by software at first.

• Debug Support

  ▆Serial Wire Debug Port – SW-DP

  ▆4 comparators for hardware breakpoints or code / literal patches

  ▆2 comparators for hardware watch points

• Package and Operation Temperature

  ▆48/64/80-pin LQFP packages

  ▆Operation temperature range: -40 °C to 85 °C