Product Features

• Core

  ▆ 32-bit Arm® Cortex®-M0+ processor core

  ▆ Up to 60 MHz operating frequency

  ▆ Single-cycle multiplication

  ▆ Integrated Nested Vectored Interrupt Controller (NVIC)

  ▆ 24-bit SysTick timer

  The Cortex®-M0+ processor is a very low gate count, highly energy efficient processor that is  intended for microcontroller and deeply embedded applications that require an area optimized,  low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb® instruction sets, single-cycle I/O ports, hardware multiplier and low latency interrupt respond time.

• On-chip Memory

  ▆ 64 KB on-chip Flash memory for instruction/data and options storage

  ▆ 8 KB on-chip SRAM

  ▆ Supports multiple booting modes

  The Arm® Cortex®-M0+ processor access and debug access share the single external interface to  external AHB peripherals. The processor access takes priority over debug access. The maximum  address range of the Cortex®-M0+ is 4 GB since it has a 32-bit bus address width. Additionally,  a pre-defined memory map is provided by the Cortex®-M0+ processor to reduce the software  complexity of repeated implementation by different device vendors. However, some regions are  used by the Arm® Cortex®-M0+ system peripherals. Refer to the Arm® Cortex®-M0+ Technical  Reference Manual for more information. Figure 2 in the Overview chapter shows the memory map  of the device, including code, SRAM, peripheral and other pre-defined regions.

• Flash Memory Controller – FMC

  ▆ Flash accelerator to obtain maximum efficiency

  ▆ 32-bit word programming with In System Programming Interface (ISP) and In Application  Programming (IAP)

  ▆ Flash protection capability to prevent illegal access

  The Flash Memory Controller, FMC, provides all the necessary functions, pre-fetch buffer and  branch cache for the embedded on-chip Flash Memory. Since the access speed of the Flash Memory  is slower than the CPU, a wide access interface with a pre-fetch buffer is provided for the Flash  Memory in order to reduce the CPU waiting time which will cause CPU instruction execution  delays. Flash Memory word programming / page erase functions are also provided.

• Reset Control Unit – RSTCU

  ▆ Supply supervisor:

  ● Power On Reset / Power Down Reset – POR / PDR

  ● Brown-Out Detector – BOD

  ● Programmable Low Voltage Detector – LVD

  The Reset Control Unit, RSTCU, has three kinds of reset, a power on reset, a system reset and an  APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.  A system reset resets the processor core and peripheral IP components with the exception of the  SW-DP controller. The resets can be triggered by external signals, internal events and the reset  generators.

• Clock Control Unit – CKCU

  ▆ External 4 to 16 MHz crystal oscillator

  ▆ External 32.768 kHz crystal oscillator

  ▆ Internal 8 MHz RC oscillator trimmed to ±2 % accuracy at 5.0 V operating voltage and 25 °C  operating temperature

  ▆ Internal 32 kHz RC oscillator

  ▆ Integrated system clock PLL

  ▆ Independent clock divider and gating bits for peripheral clock sources

  The Clock Control Unit, CKCU, provides a range of oscillator and clock functions. These include  High Speed Internal RC oscillator (HSI), High Speed External crystal oscillator (HSE), Low Speed  Internal RC oscillator (LSI), Low Speed External crystal oscillator (LSE), Phase Lock Loop (PLL),  HSE clock monitor, clock prescaler, clock multiplexer, APB clock divider and gating circuitry. The  clocks of AHB, APB and Cortex®-M0+ are derived from system clock (CK_SYS) which can come  from HSI, HSE, LSI, LSE or system PLL. Watchdog Timer (WDT) and Real Time Clock (RTC)  use either the LSI or LSE as their clock source.

• Power Management Control Unit – PWRCU

  ▆ Single VDD power supply: 2.5 V to 5.5 V

  ▆ Integrated 1.5 V LDO regulator for MCU core, peripherals and memories power supply

  ▆ Two power domains: VDD and VCORE power domains

  ▆ Two power saving modes: Sleep and Deep-Sleep modes

  Power consumption can be regarded as one of the most important issues for many embedded  system applications. Accordingly the Power Control Unit, PWRCU, in the device provides two  types of power saving modes which are the Sleep and Deep-Sleep modes. These operating modes  reduce the power consumption and allow the application to achieve the best trade-off between the  conflicting demands of CPU operating time, speed and power consumption.

• External Interrupt/Event Controller – EXTI

  ▆ Up to 16 EXTI lines with configurable trigger source and type

  ▆ All GPIO pins can be selected as EXTI trigger source

  ▆ Source trigger type includes high level, low level, negative edge, positive edge or both edges

  ▆ Individual interrupt enable, wakeup enable and status bits for each EXTI line

  ▆ Software interrupt trigger mode for each EXTI line

  ▆ Integrated deglitch filter for short pulse blocking

  The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate  a wake-up event or interrupt requests independently. Each EXTI line can also be masked  independently

• Analog to Digital Converter – ADC

  ▆ 12-bit SAR ADC engine

  ▆ Up to 1 Msps conversion rate

  ▆ Up to 8 external analog input channels for each ADC

  Two 12-bit multi-channel Analog to Digital Converter are integrated in the device. There are  multiplexed channels, which include 8 external channels on which the external analog signal can  be supplied and 4 internal channels. If the input voltage is required to remain within a specific  threshold window, the Analog Watchdog function will monitor and detect the signal. An interrupt  will then be generated to inform the device that the input voltage is higher or lower than the set  thresholds. There are three conversion modes to convert an analog signal to digital data. The A/D  conversion can be operated in one shot, continuous and discontinuous conversion mode.

• Operational Amplifier – OPA

  ▆ Rail-to-rail operational amplifier

  ▆ Fixed dedicated I/O pins

  ▆ Internal output paths to A/D converter or comparator

  Two Operational Amplifiers (OPA0~OPA1) are implemented within the device.

• Comparator – CMP

  ▆ Three Rail-to-rail comparators

  ▆ Each comparator has configurable negative inputs used for flexible voltage selection

  ● Dedicated I/O pin

  ● Internal voltage reference provided by 6-bit scaler

  ▆ Programmable hysteresis

  ▆ Programmable response speed and consumption

  ▆ Comparator output can be output to I/O or to multiple timer or ADC trigger inputs

  ▆ 6-bit scaler can be configurable to dedicated I/O for voltage reference

  ▆ Comparator n inverting input can be from CMP0N, CMPnN or CVREF

  ▆ Interrupt generation capability with wakeup from Sleep or Deep Sleep mode through the EXTI  controller

  Three general purpose comparators (CMP) are implemented within the device. They can be  configured either as standalone comparators or combined with the different kinds of peripheral IP.  Each comparator is capable of asserting interrupts to the NVIC or waking up the MCU from the  Sleep or Deep Sleep mode through EXTI wakeup event management unit.

• I/O Ports – GPIO

  ▆ Up to 40 GPIOs

  ▆ Port A, B, C are mapped as 16 external interrupts – EXTI

  ▆ Almost all I/O pins have configurable output driving current

  There are up to 40 General Purpose I/O pins, GPIO, named PA0 ~ PA15, PB0 ~ PB15 and PC0 ~ PC7 for the implementation of logic input/output functions. Each of the GPIO ports has a series of  related control and configuration registers to maximize flexibility and to meet the requirements of a  wide range of applications.

  The GPIO ports are pin-shared with other alternative functions to obtain maximum functional  flexibility on the package pins. The GPIO pins can be used as alternative functional pins by  configuring the corresponding registers regardless of the input or output pins. The external  interrupts on the GPIO pins of the device have related control and configuration registers in the  External Interrupt Control Unit, EXTI.

• Motor Control Timer – MCTM

  ▆ 16-bit up, down, up/down auto-reload counter

  ▆ 16-bit programmable prescaler that allows division of the prescaler clock source by any factor  between 1 and 65536 to generate the counter clock frequency

  ▆ Input Capture function

  ▆ Compare Match Output

  ▆ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

  ▆ Single Pulse Mode Output

  ▆ Complementary Outputs with programmable dead-time insertion

  ▆ Break input signals to assert the timer output signals in reset state or in a known state

  The Motor Control Timer Module, MCTM, consists of one 16-bit up/down-counter, four 16-bit  Capture/Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR), one 8-bit repetition  counter and several control/status registers. It can be used for a variety of purposes which include  input signal pulse width measurement, output waveform generation for signals such as compare  match outputs, PWM outputs or complementary PWM outputs with dead-time insertion. The  MCTM is capable of offering full functional support for motor control, hall sensor interfacing and  break input.

• General-Purpose Timer – GPTM

  ▆ 16-bit up, down, up/down auto-reload counter

  ▆ Up to 4 independent channels for each timer

  ▆ 16-bit programmable prescaler that allows division of the prescaler clock source by any factor  between 1 and 65536 to generate the counter clock frequency

  ▆ Input Capture function

  ▆ Compare Match Output

  ▆ PWM waveform generation with Edge-aligned and Center-aligned

  ▆ Single Pulse Mode Output

  ▆ Encoder interface controller with two inputs using quadrature decoder and Pulse/Direction Mode

  ▆ Master/Slave mode controller

  The General-Purpose Timer Module, GPTM consists of one 16-bit up/down-counter, four 16-bit  Capture/Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control  / status registers. It can be used for a variety of purposes including general time measurement,  input signal pulse width measurement, output waveform generation such as single pulse generation  or PWM output generation. The GPTM also supports an Encoder Interface using a quadrature  decoder with two inputs.

• Single Channel Timer – SCTM

  ▆ 16-bit auto-reload up-counter

  ▆ One channel for each timer

  ▆ 16-bit programmable prescaler that allows division of the prescaler clock source by any factor  between 1 and 65536 to generate the counter clock frequency

  ▆ Input Capture function

  ▆ Compare Match Output

  ▆ PWM waveform generation with Edge-aligned

  The Single-Channel Timer Module, SCTM, consists of one 16-bit up-counter, one 16-bit Capture  / Compare Register (CCR), one 16-bit Counter-Reload Register (CRR) and several control / status  registers. It can be used for a variety of purposes including general timer, input signal pulse width  measurement or output waveform generation such as PWM outputs.

• Basic Function Timer – BFTM

  ▆ 32-bit compare match up-counter – no I/O control

  ▆ One shot mode – counter stops counting when compare match occurs

  ▆ Repetitive mode – counter restarts when compare match occurs

  The Basic Function Timer Module, BFTM, is a simple 32-bit up-counting counter designed to  measure time intervals, generate one shots or generate repetitive interrupts. The BFTM can operate  in two modes, repetitive and one shot modes. In the repetitive mode, the counter will restart at each  compare match event. The BFTM also supports a one shot mode which will force the counter to  stop counting when a compare match event occurs.

• Watchdog Timer – WDT

  ▆ 12-bit down-counter with 3-bit prescaler

  ▆ Provide reset to the system

  ▆ Programmable watchdog timer window function

  ▆ Register write protection function

  The Watchdog Timer is a hardware timing circuitry that can be used to detect a system lock-up due  to software trapped in a deadlock. It includes a 12-bit down-counter, a prescaler, a WDT delta value  register, WDT operation control circuitry and a WDT protection mechanism. If the software does  not reload the counter value before a Watchdog Timer underflow occurs, a reset will be generated  when the counter underflows. In addition, a reset is also generated if the software reloads the counter  before it reaches a delta value. It means that the counter reload must occur when the Watchdog timer  value has a value within a limited window using a specific method. The Watchdog Timer counter  can be stopped when the processor is in the debug mode. The register write protection function can  be enabled to prevent an unexpected change in the Watchdog timer configuration.

• Real Time Clock – RTC

  ▆ 24-bit up-counter with a programmable prescaler

  ▆ Alarm function

  ▆ Interrupt and Wake-up control

  The Real Time Clock, RTC, circuitry includes the APB interface, a 24-bit up-counter, a control  register, a prescaler, a compare register and a status register. The RTC circuits are located in the  VCORE power domain. When the device enters the power-saving mode, the RTC counter is used as a  wakeup timer to let the system resume from the power saving mode.

• Inter-Integrated Circuit – I2 C

  ▆ Supports both master and slave modes with a frequency of up to 1 MHz

  ▆ Provides an arbitration function and clock synchronization

  ▆ Supports 7-bit and 10-bit addressing modes and general call addressing

  ▆ Supports slave multi-addressing mode using address mask function

  The I2 C module is an internal circuit allowing communication with an external I2 C interface which  is an industry standard two-wire serial interface used for connection to external hardware. These two  serial lines are known as a serial data line SDA, and a serial clock line SCL. The I2 C module provides  three data transfer rates: 100 kHz in the Standard mode, 400 kHz in the Fast mode and 1 MHz in the  Fast plus mode. The SCL period generation registers are used to setup different kinds of duty cycle  implementations for the SCL pulse.

  The SDA line which is connected directly to the I2 C bus is a bidirectional data line between the  master and slave devices and is used for data transmission and reception. The I2 C module also has  an arbitration detection and clock synchronization function to prevent situations where more than  one master attempts to transmit data to the I2 C bus at the same time.

• Serial Peripheral Interface– SPI

  ▆ Supports both master and slave modes

  ▆ Frequency of up to (fPCLK/2) MHz for the master mode and (fPCLK/3) MHz for the slave mode

  ▆ FIFO Depth: 8 levels

  ▆ Multi-master and multi-slave operation

  The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function in  both master and slave modes. The SPI interface uses 4 pins, among which are serial data input and  output lines MISO and MOSI, the clock line SCK, and the slave select line SEL. One SPI device  acts as a master who controls the data flow using the SEL and SCK signals to indicate the start of  the data communication and the data sampling rate. To receive the data bits, the streamlined data  bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data  transmission is carried out in a similar way but with the reverse sequence. The mode fault detection  provides a capability for multi-master applications.

• Universal Asynchronous Receiver Transmitter – UART

  ▆ Asynchronous serial communication operating baud-rate clock frequency up to (fPCLK/16) MHz

  ▆ Full duplex communication

  ▆ Fully programmable serial communication characteristics including:

  ● Word length: 7, 8 or 9-bit character

  ● Parity: Even, odd or no-parity bit generation and detection

  ● Stop bit: 1 or 2 stop bits generation

  ● Bit order: LSB-first or MSB-first transfer

  ▆ Error detection: Parity, overrun and frame error

  The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data  exchange using asynchronous transfer. The UART is used to translate data between parallel and  serial interfaces, and is commonly used for RS232 standard communication. The UART peripheral  function supports Line Status Interrupt. The software can detect a UART error status by reading  the UART Status & Interrupt Flag Register, URSIFR. The status includes the type and the  condition of transfer operations as well as several error conditions resulting from Parity, Overrun,  Framing and Break events.

• Universal Synchronous Asynchronous Receiver Transmitter – USART

  ▆ Supports both asynchronous and clocked synchronous serial communication modes

  ▆ Programmable baud rate clock frequency up to (fPCLK/16) MHz for Asynchronous mode and  (fPCLK/8) MHz for synchronous mode

  ▆ Full duplex communication

  ▆ Fully programmable serial communication characteristics including:

  ● Word length: 7, 8 or 9-bit character

  ● Parity: Even, odd or no-parity bit generation and detection

  ● Stop bit: 1 or 2 stop bits generation

  ● Bit order: LSB-first or MSB-first transfer

  ▆ Error detection: Parity, overrun and frame error

  ▆ Auto hardware flow control mode – RTS, CTS

  ▆ IrDA SIR encoder and decoder

  ▆ RS485 mode with output enable control

  ▆ FIFO Depth: 8-level for both receiver and transmitter

  The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible  full duplex data exchange using synchronous or asynchronous transfer. The USART is used to  translate data between parallel and serial interfaces, and is commonly used for RS232 standard  communication. The USART peripheral function supports four types of interrupt including Line  Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt  and Time Out Interrupt. The USART module includes an 8-level transmitter FIFO, (TX_FIFO) and  an 8-level receiver FIFO (RX_FIFO). The software can detect a USART error status by reading  USART Status & Interrupt Flag Register, USRSIFR. The status includes the type and the condition  of transfer operations as well as several error conditions resulting from Parity, Overrun, Framing  and Break events.

• Cyclic Redundancy Check – CRC

  ▆ Supports CRC16 polynomial: 0x8005, X16+X15+X2 +1

  ▆ Supports CCITT CRC16 polynomial: 0x1021, X16+X12+X5 +1

  ▆ Supports IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X32+X26+X23+X22+X16+X12+X11+X10+X8 +X7 +X5 +X4 +X2 +X+1

  ▆ Supports 1's complement, byte reverse & bit reverse operation on data and checksum

  ▆ Supports byte, half-word & word data size

  ▆ Programmable CRC initial seed value

  ▆ CRC computation done in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit  data

  ▆ Supports PDMA to complete a CRC computation of a block of memory

  The CRC calculation unit is an error detection technique test algorithm and is used to verify data  transmission or storage data correctness. A CRC calculation takes a data stream or a block of data  as its input and generates a 16-bit or 32-bit output remainder. Ordinarily, a data stream is suffixed  by a CRC code and used as a checksum when being sent or stored. Therefore, the received orrestored data stream is calculated by the same generator polynomial as described above. If the new  CRC code result does not match the one calculated earlier, that means the data stream contains a  data error.

• Peripheral Direct Memory Access – PDMA

  ▆ 6 channels with trigger source grouping

  ▆ 8-bit, 16-bit and 32-bit width data transfer

  ▆ Supports Linear address, circular address and fixed address modes

  ▆ 4-level programmable channel priority

  ▆ Auto reload mode

  ▆ Supports trigger sources: ADC, SPI, USART, UART, I2 C, MCTM, GPTM, SCTM and software request

  The Peripheral Direct Memory Access circuitry, PDMA, moves data between the peripherals  and the system memory on the AHB bus. Each PDMA channel has a source address, destination  address, block length and transfer count. The PDMA can exclude the CPU intervention and avoid  interrupt service routine execution. It improves system performance as the software does not need  to connect each data movement operation.

• Hardware Divider – DIV

  ▆ Signed/unsigned 32-bit divider

  ▆ Calculate in 8 clock cycles, load in 1 clock cycle

  ▆ Division by zero error Flag

  The divider is the truncated division and requires a software triggered start signal by controlling  the "START" bit in the control register. The divider calculation complete flag will be set to 1 after  8 clock cycles, however, if the divisor register data is zero during the calculation, the division by  zero error flag will be set to 1.

• Debug Support

  ▆ Serial Wire Debug Port – SW-DP

  ▆ 4 comparators for hardware breakpoint or code / literal patch

  ▆ 2 comparators for hardware watchpoints

• Package and Operation Temperature

  ▆ 48-pin LQFP package

  ▆ Operation temperature range: -40 °C to 105 °C